21,438 research outputs found

    Generalized disjunction decomposition for the evolution of programmable logic array structures

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    Evolvable hardware refers to a self reconfigurable electronic circuit, where the circuit configuration is under the control of an evolutionary algorithm. Evolvable hardware has shown one of its main deficiencies, when applied to solving real world applications, to be scalability. In the past few years several techniques have been proposed to avoid and/or solve this problem. Generalized disjunction decomposition (GDD) is one of these proposed methods. GDD was successful for the evolution of large combinational logic circuits based on a FPGA structure when used together with bi-directional incremental evolution and with (1+Ă«) evolution strategy. In this paper a modified generalized disjunction decomposition, together with a recently introduced multi-population genetic algorithm, are implemented and tested for its scalability for solving large combinational logic circuits based on Programmable Logic Array (PLA) structures

    Quantum Resonances of Weakly Linked, Mesoscopic, Superconducting Dots

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    We examine quantum properties of mesoscopic, Josephson coupled superconducting dots, in the limit that charging effects and quantization of energy levels within the dots are negligible, but quasi-particle transmission into the weak link is not. We demonstrate that quasi-particle resonances lead to current-phase relations, which deviate markedly from those of weak links connecting macroscopic superconductors. Results for the steady state dc Josephson current of two coupled dots are presented.Comment: Tex, 3 figures available on request to [email protected] (Andy Martin

    Generalized disjunction decomposition for evolvable hardware

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    Evolvable hardware (EHW) refers to self-reconfiguration hardware design, where the configuration is under the control of an evolutionary algorithm (EA). One of the main difficulties in using EHW to solve real-world problems is scalability, which limits the size of the circuit that may be evolved. This paper outlines a new type of decomposition strategy for EHW, the “generalized disjunction decomposition” (GDD), which allows the evolution of large circuits. The proposed method has been extensively tested, not only with multipliers and parity bit problems traditionally used in the EHW community, but also with logic circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library and randomly generated circuits. In order to achieve statistically relevant results, each analyzed logic circuit has been evolved 100 times, and the average of these results is presented and compared with other EHW techniques. This approach is necessary because of the probabilistic nature of EA; the same logic circuit may not be solved in the same way if tested several times. The proposed method has been examined in an extrinsic EHW system using the(1+lambda)(1 + lambda)evolution strategy. The results obtained demonstrate that GDD significantly improves the evolution of logic circuits in terms of the number of generations, reduces computational time as it is able to reduce the required time for a single iteration of the EA, and enables the evolution of larger circuits never before evolved. In addition to the proposed method, a short overview of EHW systems together with the most recent applications in electrical circuit design is provided

    A novel genetic algorithm for evolvable hardware

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    Evolutionary algorithms are used for solving search and optimization problems. A new field in which they are also applied is evolvable hardware, which refers to a self-configurable electronic system. However, evolvable hardware is not widely recognized as a tool for solving real-world applications, because of the scalability problem, which limits the size of the system that may be evolved. In this paper a new genetic algorithm, particularly designed for evolving logic circuits, is presented and tested for its scalability. The proposed algorithm designs and optimizes logic circuits based on a Programmable Logic Array (PLA) structure. Furthermore it allows the evolution of large logic circuits, without the use of any decomposition techniques. The experimental results, based on the evolution of several logic circuits taken from three different benchmarks, prove that the proposed algorithm is very fast, as only a few generations are required to fully evolve the logic circuits. In addition it optimizes the evolved circuits better than the optimization offered by other evolutionary algorithms based on a PLA and FPGA structures

    Development of New Venture Support Networks and the Role of "Promoters"

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    New Venture Support Networks (NVSN) are a political instrument for the purpose of contributing to regional economic development by fostering more and qualitatively better start-ups. NVSN bundle together different available sources of information and consultation for potential entrepreneurs, including e.g. authorities, universities, financial institutions, trade associations and private consultants. Achieving effective cooperation between such a wide range of institutions is not a simple task. The initial situation is often characterised by conflicts between the varying individual interests of the participants and the politically defined goal of fostering more and better start-ups. Moreover, since the network has been established by a political initiative for a pre-determined funding period, the actor relations within it are “artificial” (as opposed to naturally developed). Thus, the actors lack common experiences, social bonds, values and other common motivators contributing to trust-based cooperative relationships. Such relationships are a crucial factor in turning the “artificial” network into a “real” one, which continues to exist also after the political funding period is over. Our hypothesis is that certain key actors are a critical success factor in developing NVSN into “real” networks. Following the “promoter model” – an expansion of champion models that has established itself in the German innovation management literature – we suggest that there are administrative, organisational and know-how related barriers that are detrimental to the development of NVSN. The overcoming of these barriers requires a combination of different organisational resources, which the promoter model discusses in terms of three different ideal types: promoter by power, promoter by know-how, and relationship promoter. One person can act in one or more of these roles simultaneously and the roles can appear in different combinations, known as promoter structures. The specific research objectives of the proposed paper are to identify a) the types of barriers faced in the different developmental stages of NVSN and b) the roles the key actors play and the resources they use in coping with them. Our sample consists of key actors in five regional NVSN in Germany, which were established in 1998 as part of the governmental initiative “EXIST – Entrepreneurs from Universities”. The author team is also involved in one of these networks. Using a grounded theory based qualitative approach, we intend to map the development process of these NVSN with respect to the above research objectives. The contribution of the study is two-fold: 1) It presents the first application of the promoter model in the context of NVSN and produces tentative results that can be used as a basis for further research. 2) It offers practical implications to NVSN by analysing how their effectiveness and continuity could be improved by an effective use of promoter structures.

    Towards the Formal Specification and Verification of Maple Programs

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    In this paper, we present our ongoing work and initial results on the formal specification and verification of MiniMaple (a substantial subset of Maple with slight extensions) programs. The main goal of our work is to find behavioral errors in such programs w.r.t. their specifications by static analysis. This task is more complex for widely used computer algebra languages like Maple as these are fundamentally different from classical languages: they support non-standard types of objects such as symbols, unevaluated expressions and polynomials and require abstract computer algebraic concepts and objects such as rings and orderings etc. As a starting point we have defined and formalized a syntax, semantics, type system and specification language for MiniMaple
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